1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, the present invention relates to a semiconductor device including a vertical device having a pillar so as to reduce contact resistance between an upper part of the pillar and a contact connected thereto, and a method of manufacturing the same.
Priority is claimed on Japanese Patent Application No. 2009-183286, filed Aug. 6, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
In a Dynamic Random Access Memory (DRAM) of the related art, a memory cell includes a transistor and a capacitor. The increase in the integration of the DRAM has been achieved by progressing lithography technologies.
In the related art, a two-dimensional array of transistors is disposed on a semiconductor substrate. It is difficult to achieve further increase in the integration of the DRAM. A vertical transistor is suggested, which has a three-dimensional structure such that electrons can move in the direction vertical to the surface of the substrate.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2004-319808 discloses a semiconductor device including a vertical MOS transistor. A trench isolation region is provided in a silicon substrate. A channel stopper region is provided on the bottom of the isolation region. A pillar-shaped semiconductor layer is provided on the silicon substrate. A drain region is provided on the pillar-shaped semiconductor layer. A source region filling the bottom of the pillar-shaped semiconductor layer is formed in the upper surface of the silicon substrate. A gate electrode having a barrier metal is disposed on a side surface of the pillar-shaped semiconductor layer through a gate oxide film. A conductive film is provided in contact with the upper part of the drain region. The drain region is provided on the pillar-shaped semiconductor layer. An AlCu wiring layer having bather metals, which are formed on upper and lower parts thereof, are connected through a contact plug having a barrier metal.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2004-186601 discloses a semiconductor device including a vertical transistor. Pillar-shaped semiconductor layers are formed on a semiconductor substrate. A silicon oxide film is disposed on the bottom of a groove between the pillar-shaped semiconductor layers. An electrode is disposed on a gate insulating film. The electrode surrounds the peripheries of the pillar-shaped semiconductor layers. A selection gate transistor is configured as described above. Over the selection gate transistor, a floating gate is provided. A tunnel oxide film is disposed on the sidewall of each of the pillar-shaped semiconductor layers. The floating gate is disposed on the tunnel oxide film. The floating gate is separated by the tunnel oxide film from the pillar-shaped semiconductor layer. An interlayer insulating film is disposed over the control gate. The interlayer insulating film is disposed on an interlayer insulating film which covers the sidewall of the floating gate. A memory transistor is configured as described above. Over the memory transistor, the selection gate transistor is disposed. The selection gate transistor has the electrode which becomes the selection gate. The selection gate transistor is disposed on the gate insulating film. A source diffusion layer of a memory cell is disposed on the surface of the semiconductor substrate. A drain diffusion layer is disposed on the upper surface of each of the pillar-shaped semiconductor layers. The upper portion of the drain diffusion layer is not covered. An aluminum wiring is disposed covering the exposed upper part.
International Patent Publication No. WO2005/36651 discloses a semiconductor device having a buried conductor wiring which is in contact with an upper surface and with a side surface of a semiconductor protruding portion.